Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
One such FPGA, the Xilinx Virtex®-II FPGA, is described in detail in pages 33–75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
The functionality of FPGAs and CPLDs is determined by configuration data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static RAM cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell. FPGAs and CPLDs are “re-programmable” PLDS, because the circuits implemented in these devices can be changed by applying new configuration data to the device.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as ASIC devices (Application Specific Integrated Circuits). ASICs are “one-time programmable” PLDs, because once the device has been manufactured, the implemented circuit cannot be changed. Other one-time programmable PLDs include, for example, fuse and antifuse devices.
Each type of PLD has its advantages and disadvantages. For example, ASIC devices are relatively inexpensive to manufacture, once the non-recurring engineering (NRE) costs associated with their development are paid. On the other hand, re-programmable PLDs such as FPGAs require more silicon to implement the same functionality, but a user circuit can be quickly implemented in an FPGA and can be as quickly modified if future alterations are necessary.
Therefore, PLD manufacturers are beginning to experiment with mixed-fabric PLD architectures, in which two-different PLD types are included in the same device. For example, Andrews et al., in U.S. Pat. No. 6,020,755 entitled “Hybrid Programmable Gate Arrays”, describe an ASIC fabric including embedded FPGA logic cell arrays. Thus, re-programmable logic cells are included in a one-time programmable fabric.
FIG. 1 shows a mixed-fabric PLD in which a re-programmable logic portion 101 is encapsulated by a one-time programmable logic portion 102. An interface area 103 includes connections between the two programmable logic portions 101, 102. Pads 104 are included in the one-time programmable logic portion of the PLD. Therefore, connections between off-chip devices and the re-programmable logic portion 101 are made by programming one-time programmable nets through the one-time programmable logic portion of the PLD.
Testing these mixed-fabric ICs presents new challenges. For example, consider the case of an ASIC fabric (e.g., 102 in FIG. 1) in which an array of FPGA CLBs (e.g., 101 in FIG. 1) is embedded. The CLB array was previously included in a single-fabric FPGA product. Therefore, an extensive test suite already exists that thoroughly tests the functionality of the CLB array. However, in order to properly test the CLB array as part of the mixed-fabric device, it is necessary to monitor the output signals from the CLB array that occur in response to a predetermined sequence of input test data.
When testing a re-programmable device, it is standard practice to configure paths from test points within the device to output pads, where the output signals can be monitored by external test equipment. After the completion of testing, the programming in the device is cleared (e.g., by resetting the device or turning off the power) and the programmable resources used to create the pathways can be reused by the PLD user.
This approach cannot necessarily be used when testing a re-configurable array embedded in a one-time programmable fabric such as an ASIC. Because the output signals from the array are routed through the one-time programmable fabric, any connections to output pads are hard-wired using one-time programmable resources. Thus, these routing resources are no longer available for implementing user circuits. Further, the connections to the output pads are similarly hard-wired, so the output pads also become unavailable for implementing user circuits.
Therefore, it is desirable to provide alternative structures and methods for testing a re-programmable logic block embedded in a one-time programmable fabric in a PLD.
Further, a conventional tester operates at a maximum clock frequency of about 50–200 MHz (megahertz). On the other hand, some available FPGAs can operate at a frequency of about 1 GHz (gigahertz), and FPGA operating frequencies are increasing at a rapid rate. Thus, it is desirable to provide structures and methods for testing re-programmable logic blocks that allow the logic blocks to be tested at a first and higher frequency while using a tester operating at a second and lower frequency.